Strained Si1−xGex with a Ge content in a range of, for example, approximately 0.4-0.6 is a viable candidate for small geometry devices (e.g., 7 nm) and beyond. The s-SiGe can be especially advantageous for fabricating p-type field effect transistors (pFETs). While the use of strained Si (s-Si) can be beneficial when fabricating n-type FETs (nFETs), the use of Group III-V materials to fabricate nFETs is also attractive due at least to the enhanced carrier mobility that can be achieved.
One approach to achieving sub-10 nm geometry devices would be to co-integrate SiGe with a Group III-V compound semiconductor material. The Group III-V material could be a binary material such, as for example, Gallium Arsenide (GaAs) or Gallium Antimonide (GaSb). The Group III-V material could also be a tertiary material such as, for example, Indium Gallium Arsenide (InGaAs) or Indium Gallium Antimonide (InGaSb).
An ability to co-integrate s-SiGe and Group III-V semiconductor materials, and corresponding pFETs and nFETs, on a common substrate is thus a desirable goal.